A constant goal in integrated circuit fabrication is increased numbers of active components in a single integrated circuit. This can be accomplished by several techniques, but the most useful technique is minimizing the area required for particular devices in the integrated circuit. One type of circuit in which this is extremely beneficial is memory circuits. In memory circuits, data is stored in specific memory cells and the access of these memory cells is controlled by peripheral circuitry. To store a large amount of data in the memory chip, a large number of memory cells must be provided. The memory cells used in a particular integrated circuit are usually of the same type, so that area savings in the memory cell design yields large area savings in the integrated circuit as a whole. With this area savings, additional memory may be put onto a single chip or additional processing margins may be added to the process to allow for higher reliability and greater yields.
One type of memory in which space savings may be achieved by small memory cell design is the static random access memory (SRAM). In most SRAMs, each memory cell is a data latch. The usual structure of the data latch is cross-coupled inverters. Cross-coupled inverters have the output of one inverter driving the input of the other inverter and vice versa. Thus, a logical 1 or logical 0 input signal is maintained on the latch by feedback between inverters. The simplest of inverter structures is a transistor with a load device connected between the power supply and the drain and the source connected to ground. The input terminal is provided by the gate. To complete a latch, the gate of one inverter is connected to the drain of the other inverter and vice versa.
Most SRAM cells also include transfer transistors which isolate the SRAM cell when not being accessed. This prevents data being written to other cells from interfering with the data stored on a non-accessed memory cell. Thus, the normal memory cell requires four transistors and two load devices, which may be transistors. These devices have been implemented in many different ways. For example, in Minami, et al., "A New Soft Error Immune Static Memory Cell" VLSI Sympossium, p. 57 (1988), a specific memory cell using a resistor and a vertical driver transistor for greater immunity to alpha particles is described. The vertical transistor shown in FIG. 2B of Minami, et al. allows some space savings and the desired alpha particle immunity. However, the cell of Minami, et al. uses a resistor with the above-discussed area limitations.